Name
Abstract | ||
|---|---|---|
In this paper, a 12-bit pipeline Analog-to-Digital (ADC) in 0.13 mu m CMOS process with SHA-less structure is presented. Two kinds of high-speed comparators are proposed to reduce settling time of residue amplifier. Meanwhile, the foreground calibration algorithm can correct the mismatch of capacitors and alleviate the effect of finite gain of residue amplifier for better linearity. A single-to-differential reference voltage buffer which can be easily controlled by the reference voltage outside is also designed in this ADC. Measurement results show that the ADC achieves an spurious-free dynamic range (SFDR) of 83.6 dBc, a signal-to-noise ratio (SNR) of 67.16 dB and a signal-to-noise and distortion ratio (SNDR) of 66.9 dB with 9.95 MHz input signal at 120 MS/s. The integral nonlinearity (INL) and differential nonlinearity (DNL) are within +/- 0.8 LSB and +/- 0.25 LSB, respectively. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1587/elex.15.20180481 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
pipeline ADC, SHA-less, high-speed comparator, reference voltage buffer, foreground calibration | Capacitor,Computer science,12-bit,Electronic engineering,Calibration | Journal |
Volume | Issue | ISSN |
15 | 13 | 1349-2543 |
Citations | PageRank | References |
0 | 0.34 | 1 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zongkun Zhou | 1 | 0 | 1.01 |
| Min Lin | 2 | 5 | 4.11 |
| Shuigen Huang | 3 | 0 | 1.01 |
| Ruoyu Wang | 4 | 282 | 16.23 |
| Yemin Dong | 5 | 0 | 0.68 |