Name
Abstract | ||
|---|---|---|
This work presents an all-hardware real time implementation of the SIFT algorithm. The implementation exploits pipeline structures both in the keypoint extraction and in the descriptor generation stages to achieve real time requirements. To allow a feasible hardware implementations, some simplifications to the original algorithm have been required. The architecture has been synthesized on a Xilinx FPGA. It generates 3072 descriptor vectors for VGA images at 99 frames per second. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1145/3243394.3243706 | PROCEEDINGS OF THE 12TH INTERNATIONAL CONFERENCE ON DISTRIBUTED SMART CAMERAS (ICDSC'18) |
Keywords | Field | DocType |
SIFT, FPGA, real time, parallel architecture, embedded vision systems, parallel concurrent processing | Scale-invariant feature transform,Architecture,Hardware implementations,Computer science,Field-programmable gate array,Real-time computing,Exploit,Frame rate,Computer hardware,Video Graphics Array,Parallel architecture | Conference |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pablo Rubio-Ibáñez | 1 | 0 | 0.68 |
| J. Javier Martínez-Álvarez | 2 | 16 | 4.03 |
| Ginés Doménech-Asensi | 3 | 34 | 10.98 |