Paper Info
Title
A self-bandwidth switching & area-efficient PLL using multiplexer-controlled frequency selector
Abstract
In this paper, we propose a new multiplexer-based frequency selector for designing area-efficient phase locked loop (PLL) for frequency synthesis. Such reduction in the design area has been achieved by replacing conventional capacitor array in voltage controlled oscillator of this PLL by multiplexor based frequency selector. Subsequently, it has been coupled with the current-reuse voltage-controlled oscillator to reduce overall phase noise of PLL to a considerable extent. Additionally, the proposed PLL circuitry is capable of self-bandwidth switching and it is suitable for applications requiring multiple frequency bands and fast settling time. Circuit implementation of this PLL performed at 130 nm-CMOS technology-node resulted in the design area of 0.037 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , power consumption of 360µW at 0.9 GHz and a settling time of 22 µS. In comparison with the state-of-the-art implementations, our design occupies 98% smaller area and consumes 50% lesser power.
Year
DOI
Venue
2017
10.1109/ISED.2017.8303919
2017 7th International Symposium on Embedded Computing and System Design (ISED)
Keywords
Field
DocType
Phase locked loops,phase noise,voltage-controlled oscillators,complementary metal-oxide-semiconductors (CMOS) integrated circuits and very-large scale-integration (VLSI) design
Phase-locked loop,Capacitor,Settling time,Frequency-division multiplexing,Phase noise,Voltage-controlled oscillator,Electronic engineering,Multiplexer,Bandwidth (signal processing),Physics
Conference
ISBN
Citations 
PageRank 
978-1-5386-3033-4
0
0.34
References 
Authors
0
4
Name
Order
Citations
PageRank
B. Dinesh Kumar101.69
Sumit Pandey200.34
Puneet Arora300.34
Rahul Shrestha400.34