Name
Title | ||
|---|---|---|
A 50V, 1.45ns, 4.1pJ High-Speed Low-Power Level Shifter for High-Voltage DCDC Converters. |
Abstract | ||
|---|---|---|
The level shifter and the floating gate supply for high-side transistors are a major challenge in high-voltage DCDC converters. This paper presents a high-speed and power-efficient level shifter for voltages of up to 50 V, suitable for both PMOS and NMOS power FETs. A switching node falling edge detection allows both, a sensitive and safe signal detection. This enables a robust operation during steep dv/dt transitions and a power consumption as low as 4.1 pJ per switching cycle, which is a reduction of more than 40 % compared to prior art. An active clamping circuit prevents common mode displacement currents into the high-side supply. The level shifter is implemented in a 180 nm BiCMOS technology. Measurements confirm a 50 V 120 MHz high-speed operation of the level shifter with a rising/falling propagation delay of 1.45 ns/13 ns, respectively. The dv/dt robustness has been confirmed by measurements for transitions up to 6 V/ns. |
Year | Venue | Keywords |
|---|---|---|
2018 | Proceedings of the European Solid-State Circuits Conference | high-voltage level shifter,DCDC power converter,high-speed,low power |
Field | DocType | ISSN |
Logic gate,NMOS logic,Computer science,Electronic engineering,Common-mode signal,Logic level,High voltage,Signal edge,PMOS logic,Electrical engineering,Clamper | Conference | 1930-8833 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daniel Lutz | 1 | 5 | 1.26 |
| Achim Seidel | 2 | 7 | 2.99 |
| Bernhard Wicht | 3 | 19 | 9.30 |