Paper Info
Title
Highly Compact Virtual Active Counters for Per-flow Traffic Measurement.
Abstract
Per-flow traffic measurement is a fundamental problem in the era of big network data, and has been widel used in mans applications, including capacity planning, anomaly detection, load balancing, traflic engineering, etc. In order to keep up with the line speed of modern network devices (e.g., routers), per flow measurement online module is often implemented by using on -chip cache memory (such as SRAM) to minimize per-packet processing time, but on -chip SRAM is expensive and limited in size, which poses a major challenge for traffic measurement. In response, much recent research is geared towards designing highly compact data structures for approximate estimation that can provide probabilistic guarantees for per-How measurement. The state of art, called Counter Tree (CT), requires at least 2 bits per floss in memory consumption and more than 2 memory accesses per packet in processing time. In this paper, we propose a noel design of highly compact and efficient counter architecture, called Virtual Actise Counter estimation (VAC), which achieves faster processing speed (slightly more than I memory access per packet on average) and provides more accurate measurement results than CT under the same allocated memory: Moreover, VAC can perform well even with a very tight memory space (less than I bit per flow or even one fifth of a bit per Ilow). Theoretical analysis and experiments based on real network traces demonstrate the superior performance of %AC.
Year
Venue
Field
2018
IEEE INFOCOM
Computer science,Load balancing (computing),CPU cache,Networking hardware,Network packet,Static random-access memory,Capacity planning,Memory management,Computer hardware,Traffic engineering,Distributed computing
DocType
ISSN
Citations 
Conference
0743-166X
0
PageRank 
References 
Authors
0.34
0
4
Name
Order
Citations
PageRank
You Zhou195.24
Zhou, Y.2335.39
Shiping Chen319025.84
Youlin Zhang4105.26