Name
Title | ||
|---|---|---|
Simulation and modelling of long term reliability of digital circuits implemented in FPGA. |
Abstract | ||
|---|---|---|
In this work, we report on the development of a methodology for long term reliability analysis of digital circuits implemented in FPGA. For this, a simulation environment for FPGA has been extended using Python to introduce aging. The aging laws for Look-Up Tables have been integrated by introducing additional variables and equations. They accurately describe the drifts in the propagation time caused by Hot Carrier Injection and Negative Bias Temperature Instability degradation mechanisms. An analytical model of the failure time of the digital circuit as a function of the clock frequency has been proposed based on the aging law parameters. Finally, the developed methodology has been applied to a CORDIC circuit implemented in FPGA. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1016/j.microrel.2018.07.151 | MICROELECTRONICS RELIABILITY |
Keywords | Field | DocType |
Reliability,Modelling,Simulation,Digital circuits,Field programmable gate array,Negative bias thermal instability,Hot Carrier Injection | Digital electronics,Field-programmable gate array,Electronic engineering,Hot-carrier injection,CORDIC,Negative-bias temperature instability,Engineering,Propagation time,Clock rate,Python (programming language) | Journal |
Volume | ISSN | Citations |
88-90 | 0026-2714 | 0 |
PageRank | References | Authors |
0.34 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jorgue Daniel Aguirre Morales | 1 | 0 | 0.68 |
| François Marc | 2 | 9 | 5.39 |
| Bensoussan, A. | 3 | 0 | 2.03 |
| A. Durier | 4 | 0 | 1.35 |