Title
1GigaRad TID impact on 28nm HEP analog circuits
Abstract
The Total Ionizing Dose (TID) levels foreseen after the future upgrade of the CERN Large Hadron Collider (High Luminosity LHC) will heavily influence the performance of the electronics. A TID level of 1GigaRad will be accumulated in the innermost layer of the pixel detector in 10 years of operations, which could damage the readout circuits behavior with important failures in the experiments. To prevent this situation, the choice of a proper technology for the readout ASICs represents a key point. This paper deals with the characterization of single transistors and of an analog circuit, both realized in a TSMC 28nm bulk CMOS technology, after being irradiated with 1 GigaRad TID. nMOS devices result more resistant than pMOS showing a weak degradation of the electrical parameters. Nevertheless, the considerable leakage current increment is not negligible because it could affect analog circuits as that hereby presented. In the proposed analog circuit, the high radiation level induces a 20% gain reduction and an 80% slowdown of the Charge Sensitive Preamplifier time response.
Year
DOI
Venue
2018
10.1109/PRIME.2017.7974148
2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
Keywords
DocType
Volume
Analog Circuits,GigaRad,HEP experiments,Radiation
Journal
63
ISBN
Citations 
PageRank 
978-1-5090-6509-7
0
0.34
References 
Authors
3
7
Name
Order
Citations
PageRank
Federica Resta132.53
S. Gerardin2316.60
S. Mattiazzo352.90
Alessandro Paccagnella4459.45
Marcello De Matteis54217.29
Christian C. Enz645889.62
A. Baschirotto717654.55