Name
Abstract | ||
|---|---|---|
A configurable long integer multiplier tailored to subthreshold operation is presented for ultra-low-power asymmetric en/decryption in semi-passive or passive systems. The multiplier is composed of radix-4 booth de/encoders and two 544 × 16-bit partial product reduction tree arrays and reconfigurable data paths. The architecture can be configured for multiple multiplications with different bit siz... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TCSII.2018.2861922 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | Field | DocType |
Compressors,Logic gates,MOS devices,Delays,Encryption,Adders | Logic gate,Adder,16-bit,XOR gate,Arithmetic,Multiplier (economics),Electronic engineering,CMOS,Multiplication,Subthreshold conduction,Mathematics | Journal |
Volume | Issue | ISSN |
65 | 10 | 1549-7747 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Weiwei Shi | 1 | 1 | 2.10 |
| Haipeng Wang | 2 | 5 | 2.64 |
| Oliver Chiu-sing Choy | 3 | 236 | 43.80 |
| Junwei Yang | 4 | 0 | 1.35 |
| Mei Jiang | 5 | 10 | 2.84 |
| Robert K. F. Teng | 6 | 6 | 1.54 |
| Ming-Cheng Zhu | 7 | 12 | 4.23 |