Name
Abstract | ||
|---|---|---|
This brief presents a hardware design for an energy-efficient, high-speed, and 1-D median filter. Existing architectures focus on operating speeds, thus resulting in redundant power dissipation. This brief presents an algorithm and mathematical model for controlling the clock signals attached to the circuit by analyzing the behavior of the filter, which immobilizes the data in registers and reduce... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TCSII.2018.2790425 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | Field | DocType |
Computer architecture,Registers,Microprocessors,Clocks,Power demand,Filtering algorithms | Median filter,Operating frequency,Dissipation,Efficient energy use,Electronic engineering,Dynamic demand,Throughput,Computer hardware,Cycles per instruction,Mathematics,Computation | Journal |
Volume | Issue | ISSN |
65 | 11 | 1549-7747 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shih-Hsiang Lin | 1 | 0 | 0.68 |
| Pei-Yin Chen | 2 | 5 | 3.95 |
| Chang-Hsing Lin | 3 | 0 | 0.34 |