Name
Abstract | ||
|---|---|---|
This brief presents a 2-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC) with time-domain quantization, which only needs one capacitive digital-to-analog converter (DAC) array. A duplicated dynamic comparator is adopted to generate the time references. To quantize the time value, a dynamic latch-based high precision time-domain comparator is proposed. Moreover, a... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TVLSI.2018.2837030 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Threshold voltage,Time-domain analysis,Quantization (signal),Calibration,Very large scale integration,Registers,Generators | Time domain,Comparator,Computer science,Algorithm,Electronic engineering,CMOS,Spurious-free dynamic range,Redundancy (engineering),Successive approximation ADC,Quantization (signal processing),Offset (computer science) | Journal |
Volume | Issue | ISSN |
26 | 10 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lei Qiu | 1 | 0 | 0.68 |
| Chuanshi Yang | 2 | 4 | 5.14 |
| Keping Wang | 3 | 8 | 4.42 |
| Yuanjin Zheng | 4 | 328 | 72.86 |