Name
Title | ||
|---|---|---|
A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures. |
Abstract | ||
|---|---|---|
We demonstrate a 1-read/1-write two-port (2P) embedded static random access memory macro based on 8T SRAM bitcell with an effective scheme for design of testability. To achieve a smaller macro area, a differential sense amplifier is introduced to read out the data, where the reference voltage for reading 0/1 data is generated by an unselected bitcell array. In addition, we propose a screening test... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TVLSI.2018.2864267 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Random access memory,Couplings,Degradation,Timing,Logic gates,Very large scale integration,Monte Carlo methods | Sense amplifier,Logic gate,Computer science,Voltage reference,Voltage,Static random-access memory,Electronic engineering,CMOS,Macro,Very-large-scale integration | Journal |
Volume | Issue | ISSN |
26 | 11 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Makoto Yabuuchi | 1 | 49 | 12.38 |
| Yasumasa Tsukamoto | 2 | 113 | 17.90 |
| Hidehiro Fujiwara | 3 | 72 | 12.67 |
| miki tanaka | 4 | 15 | 2.03 |
| Shinji Shinji | 5 | 0 | 0.34 |
| Koji Nii | 6 | 223 | 44.78 |