Title
Scaling CMOS beyond Si FinFET: an analog/RF perspective
Abstract
FinFET has been introduced in the 22/16nm node to continue CMOS logic scaling. The very tight pitches foreseen for the coming generation necessitate the introduction of different scaling boosters. In this paper, we review how these elements affect the analog device performance. The benefits of alternative channel material for dedicated RF applications and the related integration challenges are also discussed.
Year
DOI
Venue
2018
10.1109/ESSDERC.2018.8486857
2018 48th European Solid-State Device Research Conference (ESSDERC)
Keywords
Field
DocType
analog device performance,alternative channel material,Si FinFET,CMOS logic scaling,scaling boosters,analog-RF perspective,size 22.0 nm,size 16.0 nm,Si
Gallium arsenide,Logic gate,Analog device,Communication channel,Electronic engineering,CMOS,Scaling,Materials science
Conference
ISSN
ISBN
Citations 
1930-8876
978-1-5386-5402-6
0
PageRank 
References 
Authors
0.34
0
14
Name
Order
Citations
PageRank
Bertrand Parvais1508.58
Geert Hellings200.68
Marco Simicic322.20
Pieter Weckx45216.96
Jérôme Mitard511.79
Jang, D.651.91
V. Deshpande700.34
B. van Liempc800.34
A. Veloso900.68
A. Vandooren1000.68
N. Waldron1100.68
Piet Wambacq1252996.10
Nadine Collaert1373.12
Diederik Verkest141544123.76