Paper Info
Title
Physical modeling of bitcell stability in subthreshold SRAMs for leakage-area optimization under PVT variations
Abstract
Subthreshold SRAM design is crucial for addressing the memory bottleneck in energy constrained applications. While statistical optimization can be applied based on Monte-Carlo (MC) simulation, exploration of bitcell design space is time consuming. This paper presents a framework for model-based design and optimization of subthreshold SRAM bitcells under random PVT variations. By incorporating key design and process features, a physical model of bitcell static noise margin (SNM) has been derived analytically. It captures intra-die SNM variations by the combination of a folded-normal distribution and a non-central chi-squared distribution. Validations with MC simulation show its accuracy of modeling SNM distributions down to 25mV beyond 6-sigma for typical bitcells in 28nm. Model-based tuning of subthreshold SRAM bitcells is investigated for design tradeoff between leakage, area and stability. When targeting a specific SNM constraint, we show that an optimal standby voltage exists which offers minimum bitcell leakage power - any deviation above or below increases the power consumption. When targeting a specific standby voltage, our design flow identifies bitcell instances of 12x less leakage power or 3x reductions in area as compared to the minimum-length design.
Year
DOI
Venue
2018
10.1145/3240765.3240836
ICCAD-IEEE ACM International Conference on Computer-Aided Design
Keywords
Field
DocType
SRAM,Static noise margin,Random process variations
Bottleneck,Static noise margin,Leakage (electronics),Computer science,Voltage,Static random-access memory,Electronic engineering,Design flow,Subthreshold conduction,Transistor
Conference
ISSN
ISBN
Citations 
1933-7760
978-1-4503-5950-4
0
PageRank 
References 
Authors
0.34
23
3
Name
Order
Citations
PageRank
Xin Fan1776104.55
Rui Wang213953.65
Tobias Gemmeke3496.49