Name
Title | ||
|---|---|---|
Ultralow Power, Noise Immune Stacked-Double Stage Clocked-Inverter Domino Technique For Ultradeep Submicron Technology |
Abstract | ||
|---|---|---|
High-performance system widely uses domino gates due to their high speed and low power. Everlasting demand of technology scaling increases leakage current in domino gates. These make domino circuit less immune to noise. This paper present a new energy efficient circuit technique for ultralow power consumption and higher noise immunity design for wide fan-in gates. The proposed circuit techniques reduce leakage from the evaluation network of the domino circuit with help of stacked footer approach involving clocked inverter in double stage domino. This approach has an added advantage of circuit robustness. The proposed circuit exerts less power dissipation and improved unity noise gain compared with a conventional domino circuit. The immunity is demonstrated with the help of average noise threshold energy, energy normalized ANTE (ANTE, ANTE/Energy). The simulation of the circuit is carried out by using 90nm technology in Cadence TCAD tools. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1002/cta.2524 | INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS |
Keywords | Field | DocType |
ANTE, comparator, deep submicron, delay, dynamic, stacking, VLSI | Inverter,Comparator,Domino,Electronic engineering,Power noise,Very-large-scale integration,Mathematics,Stacking | Journal |
Volume | Issue | ISSN |
46 | 11 | 0098-9886 |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sapna Rani Ghimiray | 1 | 1 | 0.71 |
| Preetisudha Meher | 2 | 1 | 0.71 |
| Pranab Kishore Dutta | 3 | 1 | 1.39 |