Name
Abstract | ||
|---|---|---|
This paper proposes a high performance physical unclonable function (PUF) implemented in a standard 65 nm CMOS process. The PUF cell is derived from SRAM-PUF cell, but it only use the NMOS or PMOS cross coupling structure with two additional access transistors. Random process variations between two cross coupling transistors are digitized to produce one bit output. Post-layout simulation results show that the 2k-bit PUF has high randomness and uniqueness, and it has some excellent features: (1) small PUF cell with a minimum feature size of 240F(2); (2) high energy efficiency of 17.3fj/b at nominal 1.2 V; (3) excellent stability: only 2.6% bit-error-rate (BER) across a wide temperature range (-40-100 degrees C) and 10% V-DD variations. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1587/elex.15.20180879 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
physical unclonable function (PUF), high performance, IoT security, circuit design | Bistability,Computer science,Internet of Things,Circuit design,Electronic engineering,Physical unclonable function | Journal |
Volume | Issue | ISSN |
15 | 21 | 1349-2543 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gang Li | 1 | 421 | 79.69 |
| Pengjun Wang | 2 | 62 | 11.93 |
| Huihong Zhang | 3 | 1 | 1.38 |