Name
Abstract | ||
|---|---|---|
In this paper, we present an efficient hardwareimplementation of a video encoder optimized for ultra low-latency, using the Logarithmic Hop Encoding algorithm. This design provides the following features: (i) A maximum marginal output latency of 23 clock cycles, (ii) small area requirements, (iii) proven rate up to 95 Millions of pixels per second in a low-end FPGA (i.e. FHD video can be streamed), (iv) on-the-fly configuration, (v) scalable architecture. The proposed design has been tested in a real video transmission scenario, where the video transmitter prototype is implemented using a ZynqBerry board, leveraging all SoC capabilities. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/FPL.2018.00067 | 2018 28th International Conference on Field Programmable Logic and Applications (FPL) |
Keywords | Field | DocType |
Video Codec,Logarithmic Hop Encoding,Soc | Synchronization,System on a chip,Computer science,Latency (engineering),Field-programmable gate array,Real-time computing,Encoder,Data compression,Codec,Encoding (memory) | Conference |
ISSN | ISBN | Citations |
1946-147X | 978-1-5386-8518-1 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tobias Alonso | 1 | 0 | 0.68 |
| Mario Ruiz | 2 | 7 | 2.29 |
| Angel Lopez Garcia-Arias | 3 | 0 | 0.34 |
| Gustavo Sutter | 4 | 82 | 9.98 |
| Jorge E. López de Vergara | 5 | 187 | 26.98 |