Name
Abstract | ||
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Memory-centric architecture, which bridges the gap between compute and memory, is considered as a promising solution to tackle the memory wall and the power wall. Such architecture integrates the computing logic and the memory resources close to each other, in order to embrace large internal memory bandwidth and reduce the data movement overhead. The closer the compute and memory resources are located, the greater these benefits become. DRAM-based in-situ accelerators [1] tightly couple processing units to every memory bitline, achieving the maximum benefits among various memory-centric architectures. However, the processing units in such architectures are typically limited to simple functions like AND/OR due to strict area and power overhead constraints in DRAMs, making it difficult to accomplish complex tasks while providing high performance.
In this paper, we address the challenge by applying stochastic computing arithmetic to the DRAM-based in-situ accelerator, targeting at the acceleration of error-tolerant applications such as deep learning. In stochastic computing, binary numbers are converted into stochastic bitstreams, which turns integer multiplications into simple bitwise AND operations, but at the expense of larger memory capacity/bandwidth demands. Stochastic computing is a perfect match for the DRAM-based in-situ accelerators because it addresses the in-situ accelerator's low performance problem by simplifying the operations, while leveraging the in-situ accelerator's advantage of large memory capacity/bandwidth. To further boost the performance and compensate for the numerical precision loss, we propose a novel Hierarchical and Hybrid Deterministic (H2D) stochastic computing arithmetic. Finally, we consider quantized deep neural network inference and training applications as a case study. The proposed architecture provides 2.3x improvement in performance per unit area compared with the binary arithmetic baseline, and 3.8x improvement over GPU. The proposed H2D arithmetic contributes 11x performance boost and 60% numerical precision improvement.
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Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/MICRO.2018.00062 | MICRO |
Keywords | Field | DocType |
DRAM,Accelerator,Stochastic Computing | Dram,Bitwise operation,Computer science,Parallel computing,Bandwidth (signal processing),Acceleration,Artificial intelligence,Deep learning,Artificial neural network,Stochastic computing,Binary number | Conference |
ISBN | Citations | PageRank |
978-1-5386-6241-0 | 10 | 0.50 |
References | Authors | |
26 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shuangchen Li | 1 | 636 | 36.82 |
| Alvin Oliver Glova | 2 | 12 | 1.54 |
| Xing Hu | 3 | 112 | 13.12 |
| Peng Gu | 4 | 142 | 11.30 |
| Dimin Niu | 5 | 609 | 31.36 |
| Krishna T. Malladi | 6 | 249 | 18.37 |
| Hongzhong Zheng | 7 | 122 | 5.94 |
| Bob Brennan | 8 | 10 | 0.50 |
| Yuan Xie | 9 | 6430 | 407.00 |