Name
Abstract | ||
|---|---|---|
This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallelization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the Maze Expansion step. Using eight threads running on eight cores, the two methods achieved speedups of 1.84× and 3.67×, respectively, compared to VPR's single-threaded routability-driven router. Removing the determinism requirement increased these respective speedups to 2.67× and 5.46×, while sacrificing the quarantee of reproducible results. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/FPL.2018.00011 | 2018 28th International Conference on Field Programmable Logic and Applications (FPL) |
Keywords | Field | DocType |
FPGA,Routing,Parallelism,Galois | Task analysis,Instruction set,Computer science,Parallel computing,Parallel processing,Field-programmable gate array,Thread (computing),Execution model,Router | Conference |
ISSN | ISBN | Citations |
1946-147X | 978-1-5386-8518-1 | 0 |
PageRank | References | Authors |
0.34 | 12 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yehdhih Ould Mohammed Moctar | 1 | 18 | 1.82 |
| Mirjana Stojilovic | 2 | 18 | 2.04 |
| Philip Brisk | 3 | 786 | 60.63 |