Paper Info
Title
Variability-Tolerant Memristor-based Ratioed Logic in Crossbar Array.
Abstract
The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this device technology, with several emerging applications including that of logic circuits. Several memristive logic families have been proposed, each with different attributes, in the current quest for energy-efficient computing systems of the future. However, limited endurance of memristor devices and variations (both cycle-to-cycle and device-to-device) are important parameters to be considered in the evaluation of such logic families. In this work we build upon an accurate physics-based model of a bipolar metal-oxide resistive RAM device (supporting parasitics of the device structure and variability of switching voltages and resistance states) and use it to show how performance of memristor-based logic circuits can de degraded owing to both variability and state-drift impact. Based on previous work on CMOS-like memristive logic circuits, we propose a memristive ratioed logic scheme, which is crossbar-compatible, i.e. suitable for in-/near-memory computing, and tolerant to device variability, while also it does not affect the device endurance since computations do not involve switching the memristor states. As a figure of merit, we compare such new logic scheme with MAGIC, focusing on the universal NOR logic gate.
Year
DOI
Venue
2018
10.1145/3232195.3232213
NANOARCH'18: PROCEEDINGS OF THE 14TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES
Keywords
Field
DocType
Ratioed logic gates,crossbar,memristor,logic design,variability-aware design
Logic synthesis,Memristor,Logic gate,Computer science,Electronic engineering,NOR logic,Logic family,Parasitic extraction,Crossbar switch,Resistive random-access memory
Conference
Citations 
PageRank 
References 
0
0.34
4
Authors
4
Name
Order
Citations
PageRank
M. Escudero100.68
Ioannis Vourkas29916.26
Antonio Rubio34216.60
Francesc Moll45514.87