Name
Abstract | ||
|---|---|---|
This paper describes low latency bimodal NRZ/ PAM-4 timing recovery. This scheme reduces latency and power consumption by eliminating the need for data equalization in the timing recovery path for inter-symbol-interference limited channels. Rather it directly equalizes the data dependent jitter by adaptively shifting the ISI effected zero crossings. The implemented prototype in 65nm CMOS supports both 10 Gb/s NRZ and 20 Gb/s PAM-4 consuming only 23 mW. The CDR achieves more than f
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">baud</sub>
/500 peaking free tracking bandwidth and adapts to optimized jitter tolerance for both PAM-4 and NRZ for the given input eye. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/ASSCC.2018.8579307 | 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) |
Keywords | Field | DocType |
Clock and Data Recovery,DDJ Equalization,Timing adaptation,Digital receiver timing recovery | Equalization (audio),Computer science,Latency (engineering),Communication channel,Electronic engineering,Bandwidth (signal processing),Latency (engineering),Jitter,Baud,Data-dependent jitter | Conference |
ISBN | Citations | PageRank |
978-1-5386-6414-8 | 1 | 0.38 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masum Hossain | 1 | 80 | 15.83 |
| Aurangozeb | 2 | 7 | 3.75 |
| Nhat Nguyen | 3 | 5 | 2.52 |