Name
Title | ||
|---|---|---|
A bulk 65nm Cortex-M0+ SoC with All-Digital Forward Body Bias for 4.3X Subthreshold Speedup |
Abstract | ||
|---|---|---|
IoT devices demand ultra-low power operation while still achieving the performance demanded by application constraints. Dynamic forward body biasing can help to achieve this by providing a speed-up during active operation without incurring a leakage penalty' during standby periods. While body biasing has been fully explored in FD-SoI technology, bulk CMOS can also benefit from efficient forward body biasing. At subthreshold voltage levels, the Low Voltage Swapped Body (LVSB) technique, in which n-well and p-well are driven to VSS and VDD respectively, helps to realize a significant speedup without incurring analog bias generation overheads. This work presents key advances to leverage LVSB, proven on a bulk 65nm subthreshold Arm Cortex-M0+ system. The system achieves a 4.3X speedup on the ULPBench benchmark at a cost of only 11% average power and 10.4% area, while showing that LVSB can be usefully applied up to 0.50V. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/ASSCC.2018.8579269 | 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC) |
Keywords | Field | DocType |
Arm,Cortex-M0+,LVSB,subthreshold,IoT,FBB | Logic gate,Leakage (electronics),Computer science,Voltage,Electronic engineering,CMOS,Subthreshold conduction,Low voltage,Speedup,Biasing | Conference |
ISBN | Citations | PageRank |
978-1-5386-6414-8 | 1 | 0.38 |
References | Authors | |
3 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pranay Prabhat | 1 | 24 | 4.69 |
| Graham Knight | 2 | 1 | 1.39 |
| Supreet Jeloka | 3 | 41 | 6.41 |
| Sheng Yang | 4 | 74 | 6.75 |
| James Myers | 5 | 32 | 7.98 |