Title
Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests
Abstract
Earlier works showed that the resolution of defect diagnosis when multiple defects are present in a chip can be improved by instructing the defect diagnosis procedure to ignore certain tests. Specifically, these procedures reduce the number of candidate faults when the defect diagnosis procedure produces large numbers of candidates. Diagnosis with a large number of candidates poses challenges to failure isolation as optical emission and electrical probing physical tools need to eliminate a large number of candidates to isolate the defects. The procedures from the earlier works improved the diagnostic resolution by reducing the number of candidates at the cost of a reduced accuracy, or a reduced overlap between the candidates and the defects present in the faulty chip. In addition, they relied on the ability to modify the defect diagnosis tool. This paper develops a procedure that improves the diagnostic resolution for multiple defects by ignoring certain tests without modifying the defect diagnosis tool. Moreover, the procedure uses a feature of commercial defect diagnosis tools to avoid losing accuracy. Experimental results for multiple defects indicate that reductions in the numbers of candidate faults are typically achieved without losing accuracy. Results are presented for benchmark circuits as well as two large logic blocks of the OpenSPARCT1 microprocessor in order to demonstrate the applicability of the procedure to such designs.
Year
DOI
Venue
2018
10.1109/DFT.2018.8602935
2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Keywords
Field
DocType
benchmark circuits,logic blocks,OpenSPARCT1 microprocessor,reduced accuracy,electrical probing physical tools,defect diagnosis procedure,multiple defect diagnosis,candidate faults,commercial defect diagnosis tools,diagnostic resolution,defect diagnosis tool
Computer science,Optical emission spectroscopy,Microprocessor,Electronic engineering,Chip,Electronic circuit,Computer engineering,Limiting
Conference
ISSN
ISBN
Citations 
1550-5774
978-1-5386-8399-6
0
PageRank 
References 
Authors
0.34
14
5
Name
Order
Citations
PageRank
Naixing Wang101.69
Irith Pomeranz28012.61
Brady Benware320.85
M. EnamulAmyeen400.34
Srikanth Venkataraman557248.05