Name
Abstract | ||
|---|---|---|
In this paper, a FPGA implementation method for convolutional neural networks of deep learning is proposed. In order to solve the problem of efficiency and speed of depth learning algorithms, a Z convolutional neural network structure is presented. The structure is easy to implement with FPGA. At the same time, in order to meet the requirement of complex multi-input and multi-output practical application system and increase the speed of calculations, a 3 dimensional Z type convolutional neural network structure is proposed, and the function of hardware circuit is verified by circuit simulation. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/IECON.2018.8592775 | IECON 2018 - 44TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY |
Keywords | Field | DocType |
Deep Learning, Convolutional Neural Network, Z-type structure, FPGA | System on a chip,Convolution,Convolutional neural network,Field-programmable gate array,Control engineering,Artificial intelligence,Engineering,Deep learning,Computer engineering | Conference |
ISSN | Citations | PageRank |
1553-572X | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Min Zhu | 1 | 14 | 12.04 |
| Qiqi Kuang | 2 | 0 | 0.34 |
| Jianjun Lin | 3 | 0 | 0.34 |
| Qihong Luo | 4 | 0 | 0.34 |
| Chunling Yang | 5 | 2 | 2.47 |
| Ming Liu | 6 | 276 | 50.00 |