Paper Info
Title
Benchmark of RRAM based Architectures for Dot-Product Computation
Abstract
Memory array architecture based on emerging non-volatile memory devices have been proposed for on-chip acceleration of dot-product computation in neural networks. As recent advances in machine learning have shown that precision reduction is a useful technique to reduce the computation and memory storage, it is desired to evaluate their hardware cost. In this paper, we use a circuit-level macro model, i.e. NeuroSim, to benchmark the circuit-level performance metrics, such as chip area, latency, and dynamic energy for the XNOR-RRAM and conventional 8-bit RRAM architectures. Both architectures are implemented to process the dot-product operation of a 512×512 synaptic matrix in sequential row-by-row and parallel read-out fashion separately. The simulation results are based on RRAM models and 32nm CMOS PDK, the energy-efficiency of the parallel XNOR-RRAM architecture could achieve 311 TOPS/W, showing at least ~15× and ~621× improvement compared to the parallel and sequential conventional 8-bit RRAM architectures respectively.
Year
DOI
Venue
2018
10.1109/APCCAS.2018.8605606
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Keywords
Field
DocType
non-volatile memory,machine learning,hardware accelerator,neuromorphic computing
Computer science,Parallel computing,Neuromorphic engineering,Electronic engineering,Chip,Non-volatile memory,Hardware acceleration,Artificial neural network,Benchmark (computing),Resistive random-access memory,Computation
Conference
ISBN
Citations 
PageRank 
978-1-5386-8241-8
0
0.34
References 
Authors
2
2
Name
Order
Citations
PageRank
Xiaochen Peng16112.17
Shimeng Yu249056.22