Name
Abstract | ||
|---|---|---|
In the past years, much of the research into hardware reverse engineering has focused on the abstraction of gate level netlists to a human readable form. However, none of the proposed methods consider a realistic reverse engineering scenario, where the netlist is physically extracted from a chip. This paper analyzes how errors caused by this extraction and the later partitioning of the netlist affect the ability to identify the functionality. Current formal verification based methods, which compare against a golden model, are incapable of dealing with such erroneous netlists. Two new methods are proposed, which focus on the idea that structural similarity implies functional similarity. The first approach uses fuzzy structural similarity matching to compare the structural characteristics of an unknown design against designs in a golden model library using machine learning. The second approach proposes a method for inexact graph matching using fuzzy graph isomorphisms, based on the functionalities of gates used within the design. For realistic error percentages, both approaches are able to match more than 90% of designs correctly. This is an important first step for hardware reverse engineering methods beyond formal verification based equivalence matching.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3287624.3288740 | ASP-DAC |
Field | DocType | Citations |
Netlist,Computer science,Reverse engineering,Circuit extraction,Fuzzy logic,Image processing,Matching (graph theory),Equivalence (measure theory),Artificial intelligence,Machine learning,Formal verification | Conference | 0 |
PageRank | References | Authors |
0.34 | 3 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Johanna Baehr | 1 | 0 | 0.68 |
| Alessandro Bernardini | 2 | 4 | 2.11 |
| Georg Sigl | 3 | 447 | 62.13 |
| Ulf Schlichtmann | 4 | 109 | 21.56 |