Name
Abstract | ||
|---|---|---|
With GPUs heading towards general-purpose, hardware caching, e.g. the first-level data (L1D) cache is introduced into the on-chip memory hierarchy for GPGPUs. However, facing the GPGPU massive multi-threading, the small L1D requires a better management for a higher hit rate to benefit the performance. In this paper, on observing the L1D usage inefficiency, such as data duplication among streaming multiprocessors (SMs) that wastes the precious L1D resources, we first propose a shared L1.5D cache that substitutes the private L1D caches in several SMs to reduce the duplicated data and in turn increase the effective cache size for each SM. We evaluate and adopt a suitable layout of L1.5D to meet the timing requirements in GPGPUs. Then, to protect the sharable data from early evictions, we propose a sharable data aware cache management, which leverages a lightweight PC-based history table to protect sharable data on cache replacement. The experiments demonstrate that the proposed design can achieve an averaged 20.1% performance improvement with an increased on-chip hit rate by 16.9% for applications with sharable data.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3287624.3287633 | ASP-DAC |
Field | DocType | Citations |
Hit rate,Data deduplication,Memory hierarchy,Computer science,CPU cache,Efficient energy use,Cache,Real-time computing,General-purpose computing on graphics processing units,Operating system,Performance improvement | Conference | 0 |
PageRank | References | Authors |
0.34 | 13 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| jianfei wang | 1 | 4 | 3.19 |
| li jiang | 2 | 30 | 7.15 |
| Jing Ke | 3 | 3 | 2.75 |
| Xiaoyao Liang | 4 | 585 | 45.81 |
| Naifeng Jing | 5 | 152 | 27.07 |