Paper Info
Title
A Compact AES Hardware Implementation Secure Against 1st-Order Side-Channel Attacks
Abstract
Efficient cryptographic implementations with desired side-channel attacks (SCA) resistance are highly required, especially for those resources-constrained devices. In this paper, we propose a very compact AES hardware implementation scheme provably secure against 1st-order SCAs. Basically, our scheme is inspired by ideas of Redundant Tower Field (RTF for short) circuit due to Ueno et al. and of private circuits due to Ishai, Sahai and Wagner (ISW for short), and is therefore named ISW-RTF. In terms of security, practical attacks on real leakages from prototype implementation show that ISW-RTF scheme is secure against 1st-order attacks and 2nd-order zero-offset attacks as well. Results of t-test leakage detection of these leakages also verify this observation. In terms of efficiency, compared with the state-of-the-art 1st-order masking scheme, our scheme outperforms at least 55.08% decreases in area, and 34.87% decreases in area-time product on three popular FPGA/ASIC devices. To the best of our knowledge, the proposed ISW-RTF scheme is the most compact one provably secure against SCA.
Year
DOI
Venue
2018
10.1109/ICCD.2018.00087
2018 IEEE 36th International Conference on Computer Design (ICCD)
Keywords
Field
DocType
Side-Channel Attacks, Masking Schemes, Compact Implementation, ISW-RTF
Leakage (electronics),Masking (art),Computer science,Field-programmable gate array,Application-specific integrated circuit,Side channel attack,Electronic circuit,Computer hardware,Cryptographic implementations
Conference
ISSN
ISBN
Citations 
1063-6404
978-1-5386-8478-8
0
PageRank 
References 
Authors
0.34
8
6
Name
Order
Citations
PageRank
Qian Zhang129043.11
YongBin Zhou213627.58
Shuang Qiu321.39
Wei Cheng4811106.56
Jingdian Ming502.70
Rui Zhang654.11