Paper Info
Title
Accurate MPSoC Prototyping Platform and Methodology for the Studying of the Linux Synchronization Barrier Slowdown Issues.
Abstract
The benefit expected from the hardware parallelism offered by Multi-Processor System on Chips (MPSoCs) is determined by the ability to design high-performance synchronization mechanisms. The complexity of modern MPSoCs does not allow anymore to design an optimized software application without confront it with the hardware platform restrictions. In this paper, we propose a methodology to study the impact of hardware contention in the synchronization barrier mechanism running on a shared memory clustered MPSoC. Taking advantage of this new observation methodology based on emulation, we identify hardware module restrictions and Linux kernel suboptimal services. We show how the introduction of delays in the thread awakening process Improves the overall synchronization mechanism. Then we detail how a combined Hardware/Software optimization for the passive wait of the synchronization barrier provides a large gain: about 60% for 64 threads running on a 64-core architecture.
Year
DOI
Venue
2018
10.1109/RSP.2018.8631996
RSP
Keywords
Field
DocType
Synchronization,Hardware,Instruction sets,Tools,Computer architecture
Computer architecture,Synchronization,Shared memory,Computer science,Instruction set,Thread (computing),Emulation,Software,MPSoC,Linux kernel
Conference
ISSN
ISBN
Citations 
1074-6005
978-1-5386-7557-1
0
PageRank 
References 
Authors
0.34
0
3
Name
Order
Citations
PageRank
Maxime France-Pillois100.34
Jérôme Martin2211.84
Frédéric Rousseau39816.06