Abstract | ||
---|---|---|
In this paper, a compact passive equalizer for differential transmission channel is designed in TSV-based three-dimensional integrated circuits (3-D ICs). The compact size of the equalizer is achieved by a square shunt metal line. Three simplified odd-mode half circuit models are proposed for groundsignal-signal-ground (G-S-S-G) type TSVs, differential on-interposer interconnects, and differential channels, respectively. Those simplified models merely consist of frequency-independent elements and can accurately predict the differential insertion losses up to 20 GHz. Moreover, the electrical parameters of the proposed serial resistance-inductance (RL) type equalizers are derived from the system transfer functions and optimized by virtue of the time-domain inter-symbol interference cancellation technique. Further, the geometrical parameters of the RL equalizers are calculated by using a genetic algorithm based multi-objective optimization method. Finally, the performance of the designed RL equalizer is validated by both frequency- and time-domain simulations for 20 Gb/s high-speed differential signaling. |
Year | DOI | Venue |
---|---|---|
2018 | 10.1109/ACCESS.2018.2884036 | IEEE ACCESS |
Keywords | Field | DocType |
Passive equalizer,through-silicon vias (TSVs),on-interposer interconnects,three-dimensional integrated circuits (3-D ICs),peak distortion analysis | Differential signaling,Topology,Capacitance,Computer science,Single antenna interference cancellation,Communication channel,Transfer function,Integrated circuit,Genetic algorithm,Equivalent circuit,Distributed computing | Journal |
Volume | ISSN | Citations |
6 | 2169-3536 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
---|---|---|---|
Kai Fu | 1 | 0 | 0.68 |
Wen-Sheng Zhao | 2 | 0 | 3.72 |
Da-Wei Wang | 3 | 0 | 3.38 |
Gaofeng Wang | 4 | 24 | 10.09 |
madhavan swaminathan | 5 | 108 | 24.63 |
Wen-yan Yin | 6 | 3 | 4.29 |