Name
Title | ||
|---|---|---|
A 0.029-Mm(2) 17-Fj/Conversion-Step Third-Order Ct Delta Sigma Adc With A Single Ota And Second-Order Noise-Shaping Sar Quantizer |
Abstract | ||
|---|---|---|
This paper presents a compact and power efficient third-order continuous-time (CT) delta-sigma (Delta Sigma) analog-todigital converter (ADC) with a single operational transconductance amplifier (OTA). A 4-bit second-order fully passive noise-shaping (NS) successive-approximation-register (SAR) ADC is employed as the quantizer while inherently provides two additional NS orders. Fabricated in 40-nm CMOS, the prototype occupies 0.029 mm(2) of active area and consumes 1.16 mW of power when clocked at 500-MHz sampling frequency. The proposed CT Delta Sigma ADC achieves a peak signal-to-noise-anddistortion ratio (SNDR) of 70.4 dB over 12.5-MHz bandwidth, yielding a Walden figure of merit (FoM) of 17 fJ/conversion-step. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/JSSC.2018.2879955 | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Keywords | DocType | Volume |
Analog-to-digital converter (ADC), coefficient scaling, continuous-time (CT) delta-sigma (Delta Sigma) ADC, excess loop delay compensation (ELDC), hybrid ADC, low-noise and high-speed comparator, passive noise shaping (NS), successive approximation register (SAR) | Journal | 54 |
Issue | ISSN | Citations |
2 | 0018-9200 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jiaxin Liu | 1 | 21 | 6.01 |
| Shaolan Li | 2 | 42 | 9.51 |
| Wen-juan Guo | 3 | 24 | 4.31 |
| Guangjun Wen | 4 | 52 | 13.05 |
| Nan Sun | 5 | 169 | 38.41 |