Paper Info
Title
A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation.
Abstract
Many cost-aware IoE devices require embedded nonvolatile memory (eNVM) to achieve high-speed read and low-power write operations for serving as code and data storage unit. Resistive random access memory (ReRAM) is a good candidate for eNVM of Internet-of-Everything (IoE) but suffers low read yield and require long read latency ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\text {CD}}$ </tex-math></inline-formula> ) against small <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R$ </tex-math></inline-formula> -ratio, large cell-resistance variations, and device-mismatch induced input offset at current-mode sense amplifier (CSA). The wide distribution in write time also causes large wasted write power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E_{\text {W}}$ </tex-math></inline-formula> ) and long NVM-stress-time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\text {STRS}}$ </tex-math></inline-formula> ). This paper proposes a bitline-current-aware small-offset CSA, using dynamic trip-point-mismatch sampling (DTPMS) scheme, to improve read yield and shorten <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\text {CD}}$ </tex-math></inline-formula> . This paper also proposes a low dc-current voltage-mode write termination (LDC-VWT) module, including SET and RESET termination circuits, to suppress <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E_{\text {W}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\text {STRS}}$ </tex-math></inline-formula> . A fabricated 65-nm 2-Mb ReRAM macro achieved <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\text {CD}}= 2.6$ </tex-math></inline-formula> ns and confirm the write-termination operations for reduction in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{\text {STRS}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E_{\text {W}}$ </tex-math></inline-formula> .
Year
DOI
Venue
2019
10.1109/JSSC.2018.2873588
J. Solid-State Circuits
Keywords
Field
DocType
Sensors,Resistance,Nonvolatile memory,Memory management,Random access memory,Periodic structures,Failure analysis
Sense amplifier,Discrete mathematics,Computer science,Computer data storage,Voltage,Electronic engineering,Non-volatile memory,Macro,Electronic circuit,Offset (computer science),Resistive random-access memory
Journal
Volume
Issue
ISSN
54
2
0018-9200
Citations 
PageRank 
References 
0
0.34
0
Authors
11
Name
Order
Citations
PageRank
Chieh-Pu Lo1222.62
Wen-Zhang Lin281.18
Wei-Yu Lin300.34
Huan-Ting Lin411.04
Tzu-Hsien Yang5224.49
Yen-Ning Chiang6131.93
Ya-Chin King712414.12
Chrong-Jung Lin801.01
Yu-Der Chih910014.94
Jonathan Chang10155.29
Meng-Fan Chang1145945.63