Name
Abstract | ||
|---|---|---|
In this paper, an unselected cell negative bias scheme (UCNB) is used to improve the read-margin of a 1D1R array. An equivalent circuit of UCNB was established, and a theoretical analysis was then conducted. The role of R
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sense</sub>
and its influence on read-margin as a function of array size are analyzed theoretically and simulated with SPICE tools. It shows that under certain R
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sense</sub>
, read-margin rises first but decreases afterward with increasing array size. In UCNB scheme, lower read-margin can be achieved at large array size. Results demonstrate the large-scale integration ability of arrays based on asymmetric memory cells. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/NVMTS.2018.8603110 | 2018 Non-Volatile Memory Technology Symposium (NVMTS) |
Keywords | Field | DocType |
UCNB,read-margin,1D1R,RRAM,array | Spice,Electronic engineering,Resistor,Materials science,Very-large-scale integration,Equivalent circuit,Resistive random-access memory | Conference |
ISBN | Citations | PageRank |
978-1-5386-7784-1 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhizhen Yu | 1 | 0 | 2.03 |
| Yichen Fang | 2 | 0 | 2.03 |
| Zongwei Wang | 3 | 1 | 2.46 |
| Yimao Cai | 4 | 9 | 7.26 |
| Ru Huang | 5 | 188 | 48.74 |
| Jintong Xu | 6 | 0 | 0.68 |