Name
Abstract | ||
|---|---|---|
We consider a digital encoding/processing system in which both the analog-to-digital converter and the digital signal processor are implemented by repeating a single fundamental design unit: the digital delay. Timing becomes an integral part of the resulting signal representation and processing, thereby promising to improve with technology scaling. System properties are studied and design considerations for a potential integrated implementation are discussed. Simulation results confirm the theory. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/TCSI.2018.2874984 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
Delays,Digital signal processors,Process control,Encoding,Delay lines,Analog-digital conversion | Signal encoding,Technology scaling,Digital signal processor,Delay,Electronic engineering,Process control,Cascade,Mathematics,Encoding (memory) | Journal |
Volume | Issue | ISSN |
66-I | 3 | 1549-8328 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sharvil Patil | 1 | 28 | 4.73 |
| Suhas Gundu Rao | 2 | 0 | 0.34 |
| Yu Chen | 3 | 517 | 49.61 |
| Y. P. Tsividis | 4 | 93 | 25.89 |