Name
Abstract | ||
|---|---|---|
Implementing scalable and effective synaptic networks will enable neuromorphic computing to deliver on its promise of revolutionizing computing. RRAM represents the most promising technology for realizing the fully connected synapse network: By using programmable resistive elements as weights, RRAM can modulate the strength of synapses in a neural network architecture. Oscillatory Neural Networks (ONNs)that are based on phase-locked loop (PLL)neurons are compatible with the resistive synapses but otherwise rather impractical. In this paper, A PLL-free ONN is implemented in 28 nm CMOS and compared to its PLL-based counterpart. Our silicon results show that the PLL-free architecture is compatible with resistive synapses, addresses practical implementation issues for improved robustness, and demonstrates favorable energy consumption compared to state-of-the-art NNs. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/ICRC.2018.8638600 | 2018 IEEE International Conference on Rebooting Computing (ICRC) |
Keywords | DocType | ISBN |
Neurons,Synapses,Phase locked loops,Biological neural networks,Delays,Clocks,Detectors | Conference | 978-1-5386-9170-0 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Thomas W. Jackson | 1 | 217 | 17.90 |
| Samuel Pagliarini | 2 | 0 | 0.34 |
| Lawrence T. Pileggi | 3 | 9 | 2.71 |