Name
Abstract | ||
|---|---|---|
<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Editor’s note:</italic>
This work aims to predict bounds on bit-error-rate performance of highspeed interconnects. The novelty lies in the characterization of timing jitter to achieve more accurate modeling of such interconnects.
<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">—Sudeep Pasricha, Colorado State University</italic> |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/MDAT.2018.2865455 | IEEE Design & Test |
Keywords | Field | DocType |
Timing jitter,Three-dimensional displays,Signal to noise ratio,Integrated circuit interconnections,Receivers,Solid modeling | Computer science,Signal-to-noise ratio,Electronic engineering,Solid modeling,Novelty,Jitter,Bit error rate | Journal |
Volume | Issue | ISSN |
36 | 1 | 2168-2356 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| L. Pizano-Escalante | 1 | 0 | 0.34 |
| Longoria-Gandara Omar | 2 | 1 | 2.06 |
| R. Parra-Michel | 3 | 23 | 5.19 |
| F. Pena-Campos | 4 | 3 | 1.77 |