Name
Abstract | ||
|---|---|---|
A new simulation model based on artificial intelligence techniques optimises the width of transistor at nanoscale level in order to reduce the power delay product is presented in this paper. The proposed model is composed from three models: graph model (GM), mathematical model (MM) and heuristic model (HM). These models cooperate together homogeneously to enhance the performance and reduce the power dissipation by selecting the optimal transistoru0027s width for each transistor in the circuit. Measurements and simulation results of the new model have been performed under 22 nm BSIM4 foundries. The average improvement in power delay product was 31% for 24-transistor full adder circuit and 43% 18-transistor C17 ISCAS benchmark circuit. The proposed model is called delay enhancement and leakage optimisation based on transistor sizing that will be appeared as (DELOTS) in the rest of the paper. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1504/IJSPM.2018.093094 | IJSPM |
Field | DocType | Volume |
Heuristic,Power–delay product,Nanoscopic scale,Adder,Leakage (electronics),Systems engineering,Dissipation,Transistor sizing,Electronic engineering,Engineering,Transistor | Journal | 13 |
Issue | Citations | PageRank |
3 | 0 | 0.34 |
References | Authors | |
0 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Abdoul Rjoub | 1 | 4 | 5.84 |
| Shihab AlKattab | 2 | 0 | 0.34 |