Paper Info
Title
An area- and energy-efficient hybrid architecture for floating-point FFT computations.
Abstract
Floating-point fast Fourier transform (FFT) has been widely expected in scientific computing and high-resolution imaging applications due to the wide dynamic range and high processing precision. However, it suffers high area and energy overhead problems in comparison to fixed-point implementations. To address these issues, this paper presents an area- and energy-efficient hybrid architecture for floating-point FFT computations. It minimizes the required arithmetic units and reduces the memory usage significantly by combining three different parts. The serial radix-4 butterfly (SR4BF) is used in the single-path delay commutator (SDC) part to minimize the required arithmetic units with 100% adder utilization ratio obtained. A modified single-path delay feedback (MSDF) architecture is proposed to achieve a tradeoff between arithmetic resources and memory usage by using the new half radix-4 butterfly (HR4BF) with 50% adder utilization ratio obtained. The intermediate caching buffer is modified accordingly in the MSDF part. By combining both the advantages on arithmetic units reducing and memory usage optimization in different parts, the optimized area and power are obtained without throughput loss. The logic synthesis results in a 65 nm CMOS technology show that the energy per FFT is about 331.5 nJ for 1024-point FFT computations at 400 MHz. The total hardware overhead is equivalent to 460k NAND2 gates.
Year
DOI
Venue
2019
10.1016/j.micpro.2018.12.007
Microprocessors and Microsystems
Keywords
Field
DocType
Fast Fourier transform (FFT),Floating-point,Hybrid architecture,Area- and energy-efficiency
Logic synthesis,Wide dynamic range,Adder,Computer science,Floating point,Efficient energy use,Parallel computing,CMOS,Fast Fourier transform,Throughput
Journal
Volume
ISSN
Citations 
65
0141-9331
1
PageRank 
References 
Authors
0.38
15
2
Name
Order
Citations
PageRank
Mingyu Wang113524.90
Zhaolin Li2289.06