Name
Abstract | ||
|---|---|---|
NVIDIA's software does not offer translation of assembly code to binary for their GPUs, since the specifications are closed-source. This work fills that gap. We develop a systematic method of decoding the Instruction Set Architectures (ISAs) of NVIDIA's GPUs, and generating assemblers for different generations of GPUs. Our framework enables cross-architecture binary analysis and transformation. Making the ISA accessible in this manner opens up a world of opportunities for developers and researchers, enabling numerous optimizations and explorations that are unachievable at the source-code level. Our infrastructure has already benefited and been adopted in important applications including performance tuning, binary instrumentation, resource allocation, and memory protection.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/CGO.2019.8661186 | Proceedings of the 2019 IEEE/ACM International Symposium on Code Generation and Optimization |
Keywords | DocType | ISSN |
CUDA, Code Generation, Code Translation and Transformation, GPU, Instruction Set Architecture (ISA) | Conference | 2164-2397 |
ISBN | Citations | PageRank |
978-1-7281-1436-1 | 0 | 0.34 |
References | Authors | |
8 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ari B. Hayes | 1 | 26 | 3.60 |
| Fei Hua | 2 | 0 | 1.35 |
| Jin Huang | 3 | 29 | 10.71 |
| Yanhao Chen | 4 | 0 | 0.34 |
| Eddy Z. Zhang | 5 | 450 | 26.12 |