Name
Abstract | ||
|---|---|---|
Power analysis attacks against lightweight ciphers are barely examined. Therefore, to verify the safety of lightweight ciphers in the future, it is important to investigate a method to verify tamper resistance against power analysis attacks. To verify the tamper resistance by performing a simulation, an extremely long processing time is required to obtain power consumption waveforms. Therefore, it is important to reduce the processing time. This study proposes a method to verify the tamper resistance of lightweight ciphers against power analysis attacks using a FPGA accelerator in order to reduce the time to obtain power consumption waveforms. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/BigDataSecurity-HPSC-IDS.2016.31 | 2016 IEEE 2nd International Conference on Big Data Security on Cloud (BigDataSecurity), IEEE International Conference on High Performance and Smart Computing (HPSC), and IEEE International Conference on Intelligent Data and Security (IDS) |
Keywords | DocType | Citations |
Security,Tamper resistance,Lightweight ciphers | Conference | 0 |
PageRank | References | Authors |
0.34 | 0 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nozaki, Y. | 1 | 5 | 11.62 |
| Kensaku Asahi | 2 | 1 | 3.78 |