Title
Testing of memristor ratioed logic (MRL) XOR gate
Abstract
This paper focuses on the production testing of Memristor Ratioed Logic (MRL) XOR gate. MRL is a family that uses memristors along with CMOS inverters to design logic gates. The two-input MRL XOR gate is investigated using the stuck at fault model for the memristors and the five-fault model for the transistors. It is shown that faults in the XOR gate produce analog output voltage values because of the circuit architecture. Therefore, a 2-bit Flash ADC is used as a special test equipment to achieve full fault coverage. Finally, four resistive short faults in the XOR gate can only be detected by monitoring the input current. It is shown that exhaustive testing is needed in order to obtain 100% fault coverage.
Year
DOI
Venue
2016
10.1109/ICM.2016.7847939
2016 28th International Conference on Microelectronics (ICM)
Keywords
Field
DocType
Memristors,MRL,production testing,XOR,fault model,fault coverage
Stuck-at fault,Memristor,Logic gate,Fault coverage,Computer science,XOR gate,Flash ADC,Electronic engineering,CMOS,Fault model
Conference
ISSN
ISBN
Citations 
2159-1679
978-1-5090-5722-1
0
PageRank 
References 
Authors
0.34
6
5
Name
Order
Citations
PageRank
A. S. Emara142.27
Ahmed H. Madian29224.50
H. H. Amer332.81
S. H. Amer472.83
M. B. AbdelHalim5457.21