Name
Abstract | ||
|---|---|---|
Field programmable Gate Arrays (FPGAs) are currently being used in the design and implementation of many modern systems. In this paper, the effect of open faults in FPGA switch matrices on the robustness of fault detection mechanisms is investigated. The error detection mechanism is studied in the context of the Duplication With Compare (DWC) technique. The programmable multiplexer with level restorer used inside the FPGA is studied for fail-safe design. An analysis for optimal level restorer transistor sizing has been derived. It is shown that the ratio between the size of the level restorer transistors and pass transistor of the programmable multiplexer should be around 5.5. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ICM.2016.7847858 | 2016 28th International Conference on Microelectronics (ICM) |
Keywords | Field | DocType |
FPGA,fault detection,switch matrix,programmable multiplexer | Pass transistor logic,Computer science,Fault detection and isolation,Matrix (mathematics),Field-programmable gate array,Error detection and correction,Electronic engineering,Robustness (computer science),Multiplexer,Transistor | Conference |
ISSN | ISBN | Citations |
2159-1679 | 978-1-5090-5722-1 | 0 |
PageRank | References | Authors |
0.34 | 9 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Manar N. Shaker | 1 | 0 | 0.34 |
| Ahmed H. Madian | 2 | 92 | 24.50 |
| M. B. AbdelHalim | 3 | 45 | 7.21 |
| S. H. Amer | 4 | 7 | 2.83 |
| A. S. Emara | 5 | 4 | 2.27 |
| H. H. Amer | 6 | 3 | 2.81 |