Paper Info
Title
Optical Interconnect And Memory Components For Disaggregated Computing
Abstract
High-performance server boards rely on multi-socket architectures for increasing the processing power density on the board level and for flattening the data center networks beyond leaf-spine architectures. Scaling, however, the number of processors per board and retaining at the same time low-latency and high-throughput metrics puts current electronic technologies into challenge. In this article, we report on our recent work carried out in the H2020 projects ICT-STREAMS and dREDBox that promotes the use of Silicon Photonic transceiver and routing modules in a powerful board-level, chip-to-chip interconnect paradigm. The proposed on-board platform leverages WDM parallel transmission with a powerful wavelength routing approach that is capable of interconnecting multiple processors with up to 25.6 Tbps on-board throughput, providing direct and collisionless any-to-any communication between multiple compute and memory sockets at low-energy 50 Gbps OOK line-rates. We demonstrate recent advances on the Si-based WDM transceiver, cyclic AWGR router and polymer-based electro-optical circuit board key-enabling technologies, discussing also potential applications in disaggregated rack-scale architectures. We also demonstrate our recent research on optical RAM technologies and optical cache memory architectures that can take advantage of the on-board interconnect technology for yielding true disintegrated computing resolving both power and memory bandwidth bottlenecks of current computational settings.
Year
DOI
Venue
2017
10.1109/ICTON.2017.8024896
2017 19TH INTERNATIONAL CONFERENCE ON TRANSPARENT OPTICAL NETWORKS (ICTON)
DocType
ISSN
Citations 
Conference
2162-7339
0
PageRank 
References 
Authors
0.34
0
6
Name
Order
Citations
PageRank
George T. Kanellos100.68
Stelios Pitris202.03
N. Terzenidis301.01
Mitsolidou, C.403.38
t alexoudi514.42
Nikos Pleros62523.69