Name
Title | ||
|---|---|---|
An efficient and scalable hardware architecture for singular value decomposition towards massive MIMO communications |
Abstract | ||
|---|---|---|
Massive multiple input multiple output (MIMO) technology plays an important role in next generation wireless communication systems. Modified Brent-Luk-Van Loan array and other parallel hardware implementations were developed for channel matrix factorization. For a large matrix size as of massive MIMO, however, previous implementations would require a large amount of hardware resource. This paper presents a hardware-efficient architecture that performs singular value decomposition of a complex matrix in arbitrary size. Eveluated on an FPGA platform, the proposed architecture results faster or competitive processing time for matrix factorization but consumes significantly less hardware resource. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/MWSCAS.2017.8053011 | Midwest Symposium on Circuits and Systems Conference Proceedings |
Keywords | Field | DocType |
massive multiple input multiple output (MIMO),singular value decomposition,hardware-efficient architecture,scalable order | Singular value decomposition,Matrix (mathematics),Computer science,Matrix decomposition,Communication channel,Field-programmable gate array,MIMO,Electronic engineering,Computer engineering,Scalability,Distributed computing,Hardware architecture | Conference |
ISSN | Citations | PageRank |
1548-3746 | 0 | 0.34 |
References | Authors | |
8 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mingda Zhou | 1 | 3 | 2.46 |
| Youjian Liu | 2 | 605 | 49.82 |
| Tian Xia | 3 | 39 | 5.50 |
| Xin-ming Huang | 4 | 356 | 46.91 |