Name
Title | ||
|---|---|---|
Test item priority estimation for high parallel test efficiency under ATE debug time constraints |
Abstract | ||
|---|---|---|
Semiconductor manufacture companies make an effort to reduce the test time for the test cost reduction until mass production starts. One of the effective test time reduction techniques is to improve the parallel test efficiency with the test program optimization by debugging on the automatic test equipment (ATE). However, given the time constraints of production schedules, the available time for the test program optimization is not enough to debug all test items at all. For this reason, it is important to select cost-effective test items in order to optimize the test program for the test time reduction. In this paper, we introduce the test item priority estimation method for high parallel test efficiency. Experimental results obtained from the actual industrial system-on-chip (SoC) circuits show that our proposed method provides the lower total test time for mass production under the same ATE debug time constraints as the cost-effective solution. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ITC-ASIA.2017.8097131 | 2017 International Test Conference in Asia (ITC-Asia) |
Keywords | Field | DocType |
parallel test efficiency,test program optimization,test item priority estimation,automatic test equipment,costs of test | Automatic test pattern generation,Test Management Approach,Automatic test equipment,Computer science,Real-time computing,Schedule,Test compression,Electronic circuit,Reliability engineering,Cost reduction,Debugging | Conference |
ISSN | ISBN | Citations |
1089-3539 | 978-1-5386-3052-5 | 0 |
PageRank | References | Authors |
0.34 | 8 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Young Woo Lee | 1 | 9 | 5.76 |
| Inhyuk Choi | 2 | 15 | 4.75 |
| Kang-Hoon Oh | 3 | 0 | 0.34 |
| James Jinsoo Ko | 4 | 0 | 0.34 |
| Sungho Kang | 5 | 12 | 6.64 |