Title
Low power FinFET content addressable memory design for 5G communication networks
Abstract
Content Addressable Memories (CAMs) are used in diverse applications, such as network protocols used in Wireless Sensor Networks (WSN), text analytics, reconfigurable computing and signal processing applications that require ultra-high speed and very low power consumption. In this work, a novel FinFET CAM using PMOS access transistors, based on PTM–MG transistor models in 22 nm and 14 nm technology is analyzed. Simulation results show that the Independent Gate (IG) FinFET CAM using PMOS access transistor exhibits a 38% improvement in the speed and 48% power consumption reduction compared to the shorted gate (SG) CAM based on 22 nm technology. Similarly, the proposed IG cell achieves a 5% improvement in speed and 50% reduction in power consumption when 14 nm technology is adopted. Hence the proposed IG cell in 14 nm has 6% improvement in speed and 59% less power consumption over 22 nm technology which is suitable for modern 5th generation communication networks.
Year
DOI
Venue
2018
10.1016/j.compeleceng.2018.03.002
Computers & Electrical Engineering
Keywords
Field
DocType
5G,Communication,SRAM,CAM,FinFET
Signal processing,Transistor model,Content-addressable memory,Computer science,Real-time computing,Electronic engineering,Transistor,PMOS logic,Wireless sensor network,Communications protocol,Reconfigurable computing
Journal
Volume
ISSN
Citations 
72
0045-7906
2
PageRank 
References 
Authors
0.41
6
2
Name
Order
Citations
PageRank
M. Arulvani120.41
M. Mohamed Ismail220.41