Name
Abstract | ||
|---|---|---|
The excellent error correction performance of Low-Density Parity Check code has made it widely used in many modern communication systems, including space communication system. This paper describes a design and FPGA implementation of a quasi-cyclic LDPC decoder based on Min-Sum Algorithm. The partially parallel design solves the contradiction between the consumption of hardware resource and decoding efficiency. The decoder achieves up to a BER of 10(-3) at 4 dB, and a throughput of 300 Mbps per iteration for a code length of 8176. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1007/978-981-10-6571-2_222 | Lecture Notes in Electrical Engineering |
Keywords | DocType | Volume |
LDPC,Min-Sum Algorithm,Partially parallel decoder,FPGA | Conference | 463 |
ISSN | Citations | PageRank |
1876-1100 | 0 | 0.34 |
References | Authors | |
4 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Honglin Zhao | 1 | 6 | 4.82 |
| Haiyue Zhang | 2 | 0 | 0.34 |