Name
Abstract | ||
|---|---|---|
IC designs have been growing exponentially in size but the number of pins have not kept the same pace. This imbalance poses a difficult challenge when a design has very limited number of test pins but still requires a high quality testing. This problem is exacerbated when additional fault models like transition delay fault model are required for testing. This paper describes how a low pin count test controller was able to meet all these requirements to test a pin limited transceiver chip used in Qualcomm Technologies Inc.'s state-of-the-art chipset. The low pin count test controller supports at-speed testing with on-chip clock controller and exceeded the test coverage requirements for both stuck-at and at-speed testing by 1.22% and 2.16% respectively. During wafer testing, this test-pin savings enabled higher parallel testing of dies using multi-site testing which reduced the test-costs by about 1.6x. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/NATW.2018.8388868 | 2018 IEEE 27th North Atlantic Test Workshop (NATW) |
Keywords | Field | DocType |
LPCT,scan,testing,compression,transceiver chip | Code coverage,Control theory,Transceiver,Computer science,Radio frequency,Low Pin Count,Wafer testing,Chipset,Computer hardware,Fault model | Conference |
ISSN | ISBN | Citations |
2573-7600 | 978-1-5386-6401-8 | 0 |
PageRank | References | Authors |
0.34 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Imtiaz Ahmed | 1 | 0 | 0.34 |
| Subhash Baraiya | 2 | 0 | 0.34 |
| Rahul Singhal | 3 | 0 | 1.35 |