Title
ShuttleNoC: Power-adaptable Communication Infrastructure for Many-core Processors
Abstract
Networks-on-chip (NoCs), as the communication infrastructure in many-core processors, has demonstrated remarkable power consumption along with the technology scaling. However, due to the temporal and spatial heterogeneity of the on-chip traffic, one critical problem is that the NoC power consumption cannot effectively adapt to the variation of its traffic intensity, also known as localized power adaptation, hence yielding a suboptimal power efficiency. Prior approaches either resort to the over-provisioned NoC design or coarse-grained bandwidth scaling to partially alleviate excessive power consumption brought by the traffic temporal or spatial heterogeneity. While in this paper, we propose a novel NoC architecture called Shuttle NoC (ShuttleNoC) to address this challenge. It leverages the link reconfiguration to enable flexible packet traversing between multiple subnetworks, and specialized punch lines to accelerate latency sensitive traffic. With the support of the dedicated power adaptation mechanisms, it is shown in the evaluation that the proposed ShuttleNoC architecture could effectively tackle the power and performance tradeoff and significantly boost the power efficiency compared with the state-of-the-art baselines.
Year
DOI
Venue
2019
10.1109/tcad.2018.2855165
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Keywords
Field
DocType
Power demand,Program processors,Bandwidth,System-on-chip,Routing,Computer architecture,Delays
Electrical efficiency,System on a chip,Computer science,Latency (engineering),Traffic intensity,Network packet,Real-time computing,Bandwidth (signal processing),Control reconfiguration,Distributed computing,Traverse
Journal
Volume
Issue
ISSN
38
8
0278-0070
Citations 
PageRank 
References 
0
0.34
0
Authors
6
Name
Order
Citations
PageRank
Hang Lu1156.70
Yisong Chang253.92
Guihai Yan317821.81
Ning Lin456.53
Xin Wei535.68
Xinrong Li61266157.76