Name
Abstract | ||
|---|---|---|
Formal methods are a promising alternative to simulation-based verification of mixed-signal systems. However, in practice, such methods fail to scale with heterogeneity and complexity of today’s analog/mixed-signal systems. Furthermore, it is unclear how they can be integrated into existing verification flows. This paper shows a path to overcome these obstacles. The idea is to use a hierarchical verification flow, in which components can be verified by formal methods or by multirun simulation. To transport verification results across hierarchies, we represent parameters and properties by affine arithmetic decision diagrams. We study to which extent this approach fulfills the needs of practical application by the verification of a phase-locked loop of an IEEE 802.15.4 transceiver system. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/tcad.2018.2864238 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Integrated circuit modeling,Computational modeling,Complexity theory,Biological system modeling,Phase locked loops,Analog circuits,Temperature sensors | Phase-locked loop,Analogue electronics,Transceiver,Affine arithmetic,Computer science,Electronic engineering,Formal methods,Hierarchy,Computer engineering | Journal |
Volume | Issue | ISSN |
38 | 10 | 0278-0070 |
Citations | PageRank | References |
1 | 0.43 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Carna Zivkovic | 1 | 1 | 1.11 |
| Christoph Grimm | 2 | 6 | 2.06 |
| M. Olbrich | 3 | 11 | 4.28 |
| Oliver Scharf | 4 | 1 | 0.43 |
| Barke, E. | 5 | 66 | 12.44 |