Name
Abstract | ||
|---|---|---|
Placement and packing are two important but separated optimization steps in a conventional field programmable gate array (FPGA) implementation flow. A packing engine clusters logic elements, like lookup tables and flip-flops, into configurable logic blocks, while a placement engine determines their physical locations in FPGA layouts. This paper presents a new paradigm for FPGA placement without an... |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/TCAD.2018.2877017 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Field programmable gate arrays,Table lookup,Law,Engines,Benchmark testing | Lookup table,Computer science,Parallel computing,Field-programmable gate array,Electronic engineering,Benchmark (computing) | Journal |
Volume | Issue | ISSN |
38 | 11 | 0278-0070 |
Citations | PageRank | References |
2 | 0.37 | 0 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wuxi Li | 1 | 36 | 6.03 |
| David Z. Pan | 2 | 2653 | 237.64 |